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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1998 mos integrated circuit m m m m pd16634a 300-output tft-lcd source driver (compatible with 64 gray scale) data sheet the mark ? ? ? ? shows major revised points. document no. s12595ej2v0ds00 (2nd edition) date published march 1999 ns cp (k) printed in japan description the m pd16634a is a source driver for tft-lcds capable of dealing with displays 64 gray scales. data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values g -corrected by an internal d/a converter and 5-by-2 external power modules. because the output dynamic range is as large as v ss2 +0.1 v to v dd2 - 0.1 v, level inversion operation of the lcds common electrode is rendered unnecessary. also to be able to deal with dot-line inversion when mounted on a single side, this source driver equipped with a built-in 6-bit d/a converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. assuring a maximum clock frequent of 40 mhz when drivng at 3.0 v, this driver is applicable to xga-standard tft-lcd panels. features 300 outputs cmos level input input of 6 bits (gradation data) by 6 dots capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a d/a converter output dynamic range : v ss2 +0.1 v to v dd2 - 0.1 v logic part supply voltage (v dd1 ) : 3.3 v 0.3 v driver part supply voltage (v dd2 ) : 8.0 v 0.5 v high-speed data transfer: f max =40 mhz min.(internal data transfer rate when operating at 3.0 v) output voltage polarity inversion is possible (pol) display data inversion function (pol2) single bank arrangement is possible(loaded with slim tcp). ordering information part number package m pd16634an-xxx tcp (tab package) remark the tcps external shape is customized. to order your tcps external shape, please contact a nec salesperson. h h h h
data sheet s12595ej2v0ds00 2 m m m m pd16634a 1. block diagram 50-bit bidirectional shift register c 1 c 2 c 49 c 50 data register latch level shifter d/a converter voltage follower output s 1 s 2 s 3 s 300 v 0 - v 9 pol d 00 - d 05 d 10 - d 15 d 20 - d 25 sthr r,/l clk stb sthl v dd1 v ss1 v dd2 v ss2 d 30 - d 35 d 40 - d 45 d 50 - d 55 pol2 remark /xxx indicates active low si gnal.
data sheet s12595ej2v0ds00 3 m m m m pd16634a 2. relationship between output circuit and d/a converter v 0 v 4 v 5 v 9 5 5 s 1 s 2 s 299 s 300 6-bit d/a converter multi- plexer pol h
data sheet s12595ej2v0ds00 4 m m m m pd16634a 3. pin configuration ( m m m m pd16634an-xxx) s 300 s 299 s 298 s 297 v ss2 v dd2 v ss1 r,/l pol stb d 55 d 54 d 53 d 52 d 51 d 50 d 45 d 44 d 43 d 42 d 41 d 40 d 35 d 34 d 33 d 32 d 31 sthl v 9 v 8 v 7 v 6 v 5 v 4 v 3 v 2 v 1 v 0 clk sthr d 30 d 25 d 24 d 23 d 22 d 21 d 20 d 15 d 14 d 13 d 12 d 11 d 10 d 05 d 04 d 03 d 02 d 01 d 00 pol2 test v dd1 v dd2 v ss2 s 4 s 3 s 2 s 1 (copper plated surface) caution this figure does not specify the tcp package. therefore pol2 pins can be reduced by opening or short-circuiting to v ss2 by tcp wiring. pol2 pin can short to v ss1 on tcp. so when you not use data inversion function, can reduce input pins.
data sheet s12595ej2v0ds00 5 m m m m pd16634a 4. pin functions pin symbol pin name description s 1 to s 300 driver output the d/a converted 64-gray-scale analog voltage is output d 00 to d 05 display data input the display data is input with a width of 36 bits, viz., the gray scale data d 10 to d 15 (6 bits) by 6 dots (2 pixels). d 20 to d 25 d x0 : lsb, d x5 : msb d 30 to d 35 d 40 to d 45 d 50 to d 55 r,/l shift direction switching input these refer to the start pulse input/output pins when cascades are connected. the shift directions of the shift registers are as follows. r,/l = h : sthr input, s 1 ? s 300 , sthl output r,/l = l : sthl input, s 300 ? s 1 , sthr output sthr right shift start pulse input/output r,/l = h : becomes the start pulse input pin. r,/l = l : becomes the start pulse output pin. sthl left shift start pulse input/output r,/l = h : becomes the start pulse input pin. r,/l = l : becomes the start pulse output pin. clk shift clock input refers to the shift registers shift clock input. the display data is incorporated into the data register at the rising edge. at the rising edge of the 50th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. the initial- level drivers 50th clock becomes valid as the next-level drivers start pulse is input. if 52 clock pulses are input after input of the start pulse, input of display data is halted automatically. the contents of the shift register are cleared at the stbs rising edge. stb latch input the contents of the data register are transferred to the latch at the rising edge. and, at the falling edge, the gray scale voltage is supplied to the driver. it is necessary to ensure input of one pulse per horizontal period. pol polarity input pol = l ; the s 2n-1 output uses v 0 to v 4 as the reference supply; and the s 2n output uses v 5 to v 9 as the reference supply. pol = h ; the s 2n-1 output uses v 5 to v 9 as the reference supply; and the s 2n output uses v 0 to v 4 as the reference supply. s 2n-1 indicates the odd output; and s 2n indicates the even output. input of the pol signal is allowed the setup time (t pol-stb ) with respect to stbs rising edge. pol2 data inversion input pol2 = h : display data is inverted. pol2 = l : display data is not inverted. v 0 to v 9 g -corrected power supplies input the g -corrected power supplies from outside by using operational amplifier. make sure to maintain the following relationships. during the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. v dd2 > v 0 > v 1 > v 2 > v 3 > v 4 > v 5 > v 6 > v 7 > v 8 > v 9 > v ss2 test test pin set it to open. v dd1 logic circuit power supply 3.3 v 0.3 v v dd2 driver circuit power supply 8.0 v 0.5 v v ss1 logic ground grounding v ss2 driver ground grounding cautions 1. the power start sequence must be v dd1 , logic input, and v dd2 & v 0 to v 9 in that order. reverse this sequence to shut down.(simultaneous power application to v dd2 and v 0 to v 9 is possible.) 2. to stabilize the supply voltage, please be sure to insert 0.1 m m m m f bypass capacitor between v dd1 -v ss1 and v dd2 -v ss2 . furthermore, for increase precision of the d/a converter, insertion of a bypass capacitor of about 0.01 m m m m f is also advised between the g g g g -corrected power supply terminals(v 0 ,v 1 ,v 2 ...,v 9 ) and v ss2 . 3. we recommend to use operational amplifier to lower input impedance of g g g g -corrected voltage.
data sheet s12595ej2v0ds00 6 m m m m pd16634a 5. relationhip between input data and output voltage value this product incorporates a 6-bit d/a converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the lcds counter electrode (common electrode) voltage. the d/a converter consists of ladder resistors and switches. the ladder resistors r 0 to r 62 are so designed that the ratios between the lcd panels g -corrected voltages and v 0 to v 63 , v 0 to v 63 are roughly equal; and their respective resistance values are as shown in table 6-1. among the 5-by 2 g -corrected voltages, input gray scale voltages of the same polarity with respect to the common voltage, for the respective five g -corrected voltages of v 0 to v 4 and v 5 to v 9 . if fine gray scale voltage precision is not necessary, the voltage follower circuit supplied to the g -corrected power supplies v 1 to v 3 and v 6 to v 8 can be deleted. figure 5-1 shows the relationship between the driving voltages such as liquid-crystal driving voltages v dd2 and v ss2 , common electrode potential v com , and g -corrected voltages v 0 to v 9 and the input data. be sure to maintain the voltage relationships of v dd2 > v 0 > v 1 > v 2 > v 3 > v 4 > v 5 > v 6 > v 7 > v 8 > v 9 > v ss2 . figure 6-1 and 6-2 show the relationship between the input data and the output data. this driver ic is designed for single-sided mounting. therefore, please do not use it for g -corrected power supply level inversion in double-sided mounting. figure 5-1. relationship between input data and output voltage v dd2 v 1 v 2 v 3 v 4 v com v 5 v 6 v 7 v 8 v ss2 00 08 10 18 20 28 30 38 3f input data (hex) 16 16 16 15 15 16 16 16 split interval v 0 v 9 h
data sheet s12595ej2v0ds00 7 m m m m pd16634a 6. resistor strings figure 6-1. relationship between input data and output voltage : v dd2 > v 0 > v 1 > v 2 > v 3 > v 4 > v 5 , pol2 = l v 0 v 1 v 2 v 3 v 15 v 16 v 17 v 31 v 32 v 33 v 47 v 48 v 49 v 61 v 62 v 63 v 63 v 62 v 0 r 0 r 1 r 2 r 3 r 14 r 15 r 16 r 17 r 30 r 31 v 2 r 32 r 33 r 46 r 47 v 3 r 48 r 49 r 60 r 61 r 62 r 62 v 1 v 5 v 4 data d x5 d x4 d x3 d x2 d x1 d x0 output voltage 00h 000000 v 0 v 0 01h 000001 v 1 v 1 + (v 0 C v 1 ) 7250/8050 02h 000010 v 2 v 1 + (v 0 C v 1 ) 6500/8050 03h 000011 v 3 v 1 + (v 0 C v 1 ) 5800/8050 04h 000100 v 4 v 1 + (v 0 C v 1 ) 5150/8050 05h 000101 v 5 v 1 + (v 0 C v 1 ) 4550/8050 06h 000110 v 6 v 1 + (v 0 C v 1 ) 4000/8050 07h 000111 v 7 v 1 + (v 0 C v 1 ) 3450/8050 08h 001000 v 8 v 1 + (v 0 C v 1 ) 2950/8050 09h 001001 v 9 v 1 + (v 0 C v 1 ) 2450/8050 0ah 001010 v 10 v 1 + (v 0 C v 1 ) 2050/8050 0bh 001011 v 11 v 1 + (v 0 C v 1 ) 1650/8050 0ch 001100 v 12 v 1 + (v 0 C v 1 ) 1300/8050 0dh 001101 v 13 v 1 + (v 0 C v 1 ) 950/8050 0eh 001110 v 14 v 1 + (v 0 C v 1 ) 600/8050 0fh 001111 v 15 v 1 + (v 0 C v 1 ) 300/8050 10h 010000 v 16 v 1 11h 010001 v 17 v 2 + (v 1 C v 2 ) 2450/2750 12h 010010 v 18 v 2 + (v 1 C v 2 ) 2200/2750 13h 010011 v 19 v 2 + (v 1 C v 2 ) 1950/2750 14h 010100 v 20 v 2 + (v 1 C v 2 ) 1700/2750 15h 010101 v 21 v 2 + (v 1 C v 2 ) 1500/2750 16h 010110 v 22 v 2 + (v 1 C v 2 ) 1300/2750 17h 010111 v 23 v 2 + (v 1 C v 2 ) 1100/2750 18h 011000 v 24 v 2 + (v 1 C v 2 ) 950/2750 19h 011001 v 25 v 2 + (v 1 C v 2 ) 800/2750 1ah 011010 v 26 v 2 + (v 1 C v 2 ) 650/2750 1bh 011011 v 27 v 2 + (v 1 C v 2 ) 500/2750 1ch 011100 v 28 v 2 + (v 1 C v 2 ) 400/2750 1dh 011101 v 29 v 2 + (v 1 C v 2 ) 300/2750 1eh 011110 v 30 v 2 + (v 1 C v 2 ) 200/2750 1fh 011111 v 31 v 2 + (v 1 C v 2 ) 100/2750 20h 100000 v 32 v 2 21h 100001 v 33 v 3 + (v 2 C v 3 ) 1500/1600 22h 100010 v 34 v 3 + (v 2 C v 3 ) 1400/1600 23h 100011 v 35 v 3 + (v 2 C v 3 ) 1300/1600 24h 100100 v 36 v 3 + (v 2 C v 3 ) 1200/1600 25h 100101 v 37 v 3 + (v 2 C v 3 ) 1100/1600 26h 100110 v 38 v 3 + (v 2 C v 3 ) 1000/1600 27h 100111 v 39 v 3 + (v 2 C v 3 ) 900/1600 28h 101000 v 40 v 3 + (v 2 C v 3 ) 800/1600 29h 101001 v 41 v 3 + (v 2 C v 3 ) 700/1600 2ah 101010 v 42 v 3 + (v 2 C v 3 ) 600/1600 2bh 101011 v 43 v 3 + (v 2 C v 3 ) 500/1600 2ch 101100 v 44 v 3 + (v 2 C v 3 ) 400/1600 2dh 101101 v 45 v 3 + (v 2 C v 3 ) 300/1600 2eh 101110 v 46 v 3 + (v 2 C v 3 ) 200/1600 2fh 101111 v 47 v 3 + (v 2 C v 3 ) 100/1600 30h 110000 v 48 v 3 31h 110001 v 49 v 4 + (v 3 C v 4 ) 3350/3450 32h 110010 v 50 v 4 + (v 3 C v 4 ) 3250/3450 33h 110011 v 51 v 4 + (v 3 C v 4 ) 3150/3450 34h 110100 v 52 v 4 + (v 3 C v 4 ) 3050/3450 35h 110101 v 53 v 4 + (v 3 C v 4 ) 2950/3450 36h 110110 v 54 v 4 + (v 3 C v 4 ) 2800/3450 37h 110111 v 55 v 4 + (v 3 C v 4 ) 2650/3450 38h 111000 v 56 v 4 + (v 3 C v 4 ) 2500/3450 39h 111001 v 57 v 4 + (v 3 C v 4 ) 2300/3450 3ah 111010 v 58 v 4 + (v 3 C v 4 ) 2100/3450 3bh 111011 v 59 v 4 + (v 3 C v 4 ) 1850/3450 3ch 111100 v 60 v 4 + (v 3 C v 4 ) 1600/3450 3dh 111101 v 61 v 4 + (v 3 C v 4 ) 1300/3450 3eh 111110 v 62 v 4 + (v 3 C v 4 ) 800/3450 3fh 111111 v 63 v 4
data sheet s12595ej2v0ds00 8 m m m m pd16634a figure 6-2. relationship between input data and output voltage : v 4 > v 5 > v 6 > v 7 > v 8 > v 9 > v ss2 , pol2 = l v 63 v 62 v 61 v 49 v 48 v 47 v 33 v 32 v 31 v 17 v 16 v 15 v 3 v 2 v 1 v 0 v 4 v 5 r 62 r 61 r 60 r 49 r 48 v 6 r 47 r 46 r 33 r 32 v 7 r 31 r 30 r 17 r 16 r 15 r 14 r 3 r 2 r 1 r 0 v 9 v 8 r 62 v 62 v 63 data d x5 d x4 d x3 d x2 d x1 d x0 output voltage 00h 0 0 0 0 0 0 v 0 v 9 01h 0 0 0 0 0 1 v 1 v 9 + (v 8 C v 9 ) 800/8050 02h 0 0 0 0 1 0 v 2 v 9 + (v 8 C v 9 ) 1550/8050 03h 0 0 0 0 1 1 v 3 v 9 + (v 8 C v 9 ) 2250/8050 04h 0 0 0 1 0 0 v 4 v 9 + (v 8 C v 9 ) 2900/8050 05h 0 0 0 1 0 1 v 5 v 9 + (v 8 C v 9 ) 3500/8050 06h 0 0 0 1 1 0 v 6 v 9 + (v 8 C v 9 ) 4050/8050 07h 0 0 0 1 1 1 v 7 v 9 + (v 8 C v 9 ) 4600/8050 08h 0 0 1 0 0 0 v 8 v 9 + (v 8 C v 9 ) 5100/8050 09h 0 0 1 0 0 1 v 9 v 9 + (v 8 C v 9 ) 5600/8050 0ah 0 0 1 0 1 0 v 10 v 9 + (v 8 C v 9 ) 6000/8050 0bh 0 0 1 0 1 1 v 11 v 9 + (v 8 C v 9 ) 6400/8050 0ch 0 0 1 1 0 0 v 12 v 9 + (v 8 C v 9 ) 6750/8050 0dh 0 0 1 1 0 1 v 13 v 9 + (v 8 C v 9 ) 7100/8050 0eh 0 0 1 1 1 0 v 14 v 9 + (v 8 C v 9 ) 7450/8050 0fh 0 0 1 1 1 1 v 15 v 9 + (v 8 C v 9 ) 7750/8050 10h 0 1 0 0 0 0 v 16 v 8 11h 0 1 0 0 0 1 v 17 v 8 + (v 7 C v 8 ) 300/2750 12h 0 1 0 0 1 0 v 18 v 8 + (v 7 C v 8 ) 550/2750 13h 0 1 0 0 1 1 v 19 v 8 + (v 7 C v 8 ) 800/2750 14h 0 1 0 1 0 0 v 20 v 8 + (v 7 C v 8 ) 1050/2750 15h 0 1 0 1 0 1 v 21 v 8 + (v 7 C v 8 ) 1250/2750 16h 0 1 0 1 1 0 v 22 v 8 + (v 7 C v 8 ) 1450/2750 17h 0 1 0 1 1 1 v 23 v 8 + (v 7 C v 8 ) 1650/2750 18h 0 1 1 0 0 0 v 24 v 8 + (v 7 C v 8 ) 1800/2750 19h 0 1 1 0 0 1 v 25 v 8 + (v 7 C v 8 ) 1950/2750 1ah 0 1 1 0 1 0 v 26 v 8 + (v 7 C v 8 ) 2100/2750 1bh 0 1 1 0 1 1 v 27 v 8 + (v 7 C v 8 ) 2250/2750 1ch 0 1 1 1 0 0 v 28 v 8 + (v 7 C v 8 ) 2350/2750 1dh 0 1 1 1 0 1 v 29 v 8 + (v 7 C v 8 ) 2450/2750 1eh 0 1 1 1 1 0 v 30 v 8 + (v 7 C v 8 ) 2550/2750 1fh 0 1 1 1 1 1 v 31 v 8 + (v 7 C v 8 ) 2650/2750 20h 1 0 0 0 0 0 v 32 v 7 21h 1 0 0 0 0 1 v 33 v 7 + (v 6 C v 7 ) 100/1600 22h 1 0 0 0 1 0 v 34 v 7 + (v 6 C v 7 ) 200/1600 23h 1 0 0 0 1 1 v 35 v 7 + (v 6 C v 7 ) 300/1600 24h 1 0 0 1 0 0 v 36 v 7 + (v 6 C v 7 ) 400/1600 25h 1 0 0 1 0 1 v 37 v 7 + (v 6 C v 7 ) 500/1600 26h 1 0 0 1 1 0 v 38 v 7 + (v 6 C v 7 ) 600/1600 27h 1 0 0 1 1 1 v 39 v 7 + (v 6 C v 7 ) 700/1600 28h 1 0 1 0 0 0 v 40 v 7 + (v 6 C v 7 ) 800/1600 29h 1 0 1 0 0 1 v 41 v 7 + (v 6 C v 7 ) 900/1600 2ah 1 0 1 0 1 0 v 42 v 7 + (v 6 C v 7 ) 1000/1600 2bh 1 0 1 0 1 1 v 43 v 7 + (v 6 C v 7 ) 1100/1600 2ch 1 0 1 1 0 0 v 44 v 7 + (v 6 C v 7 ) 1200/1600 2dh 1 0 1 1 0 1 v 45 v 7 + (v 6 C v 7 ) 1300/1600 2eh 1 0 1 1 1 0 v 46 v 7 + (v 6 C v 7 ) 1400/1600 2fh 1 0 1 1 1 1 v 47 v 7 + (v 6 C v 7 ) 1500/1600 30h 1 1 0 0 0 0 v 48 v 6 31h 1 1 0 0 0 1 v 49 v 6 + (v 5 C v 6 ) 100/3450 32h 1 1 0 0 1 0 v 50 v 6 + (v 5 C v 6 ) 200/3450 33h 1 1 0 0 1 1 v 51 v 6 + (v 5 C v 6 ) 300/3450 34h 1 1 0 1 0 0 v 52 v 6 + (v 5 C v 6 ) 400/3450 35h 1 1 0 1 0 1 v 53 v 6 + (v 5 C v 6 ) 500/3450 36h 1 1 0 1 1 0 v 54 v 6 + (v 5 C v 6 ) 650/3450 37h 1 1 0 1 1 1 v 55 v 6 + (v 5 C v 6 ) 800/3450 38h 1 1 1 0 0 0 v 56 v 6 + (v 5 C v 6 ) 950/3450 39h 1 1 1 0 0 1 v 57 v 6 + (v 5 C v 6 ) 1150/3450 3ah 1 1 1 0 1 0 v 58 v 6 + (v 5 C v 6 ) 1350/3450 3bh 1 1 1 0 1 1 v 59 v 6 + (v 5 C v 6 ) 1600/3450 3ch 1 1 1 1 0 0 v 60 v 6 + (v 5 C v 6 ) 1850/3450 3dh 1 1 1 1 0 1 v 61 v 6 + (v 5 C v 6 ) 2150/3450 3eh 1 1 1 1 1 0 v 62 v 6 + (v 5 C v 6 ) 2650/3450 3fh 1 1 1 1 1 1 v 63 v 5
data sheet s12595ej2v0ds00 9 m m m m pd16634a table 6-1. ladder resistance values (r 0 to r 62 ) : reference value resistor name r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7 r 8 r 9 r 10 r 11 r 12 r 13 r 14 r 15 r 16 r 17 r 18 r 19 r 20 r 21 r 22 r 23 r 24 r 25 r 26 r 27 r 28 r 29 r 30 r 31 resistance value ( w ) 800 750 700 650 600 550 550 500 500 400 400 350 350 350 300 300 300 250 250 250 200 200 200 150 150 150 150 100 100 100 100 100 resistor name r 32 r 33 r 34 r 35 r 36 r 37 r 38 r 39 r 40 r 41 r 42 r 43 r 44 r 45 r 46 r 47 r 48 r 49 r 50 r 51 r 52 r 53 r 54 r 55 r 56 r 57 r 58 r 59 r 60 r 61 r 62 total resistance value ( w ) 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 150 150 150 200 200 250 250 300 500 800 15850 v 0 , v 9 v 1 , v 8 v 2 , v 7 v 4 , v 5 v 3 , v 6 v 2 , v 7
data sheet s12595ej2v0ds00 10 m m m m pd16634a 7. relationship between input data and output pin data format : 6 bits x 2 rgbs (6 dots) input width : 36 bits (2-pixel data) (1) r,/l = h (right shift) output s 1 s 2 s 3 s 4 s 5 ? s 299 s 300 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 d 40 to d 45 ? d 40 to d 45 d 50 to d 55 (2) r,/l = l (left shift) output s 1 s 2 s 3 s 4 s 5 ? s 299 s 300 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 d 40 to d 45 ? d 40 to d 45 d 50 to d 55 pol s 2n-1 s 2n lv 0 to v 4 v 5 to v 9 hv 5 to v 9 v 0 to v 4 remark s 2n-1 (odd output), s 2n (even output)n = 1,2,.......,150 8. relationship between stb, pol, and output waveform the output voltage is written to the lcd panel synchronized with the stb falling edge. stb pol s 2nC1 s 2n selected voltage of v 0 to v 4 selected voltage of v 5 to v 9 selected voltage of v 0 to v 4 selected voltage of v 5 to v 9 selected voltage of v 0 to v 4 selected voltage of v 5 to v 9 hi-z hi-z hi-z
data sheet s12595ej2v0ds00 11 m m m m pd16634a 9. cautions about frame inversion in the case of dot inversion, n frame last line and (n+1) frame first line is the same polarity. when write the same polarity twice; there are two cases as follows. (1) last line output in n frame > first line output in (n+1) frame ? positive to write (2) last line output in n frame < first line output in (n+1) frame ? not possible to write m pd16634a has charge buffer and discharge buffer, so need to inversion polarity and write in the case of both ways. stb n frame last line second line first line vertical intervals (n+1) frame (n+1) frame discharge buffer charge buffer v com hi-z hi-z hi-z pol s 2n stb n frame last line second line first line vertical intervals (n+1) frame (n+1) frame v com hi-z hi-z hi-z pol s 2n hi-z
data sheet s12595ej2v0ds00 12 m m m m pd16634a 10. electrical specifications absolute maximum ratings (t a = 25 c,v ss1 = v ss2 = 0 v) parameter symbol ratings unit logic part supply voltage v dd1 C0.5 to +5.0 v driver part supply voltage v dd2 C0.5 to +10.0 v logic part input voltage v i1 C0.5 to v dd1 + 0.5 v driver part input voltage v i2 C0.5 to v dd2 + 0.5 v logic part output voltage v o1 C0.5 to v dd1 + 0.5 v driver part output voltage v o2 C0.5 to v dd2 + 0.5 v operating ambient temperature t a C10 to +75 c storage temperature t stg C55 to +125 c caution if the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product within the range of the absolute maximum ratings. recommended operating range (t a = C10 to +75 c, v ss1 = v ss2 = 0 v) parameter symbol min. typ. max. unit logic part supply voltage v dd1 3.0 3.3 3.6 v driver part supply voltage v dd2 7.5 8.0 8.5 v high-level input voltage v ih 0.7v dd1 v dd1 v low-level input voltage v il 00.3v dd1 v g -corrected supply voltage v 0 to v 9 v ss2 v dd2 v driver part output voltage v o v ss2 + 0.1 v dd2 C 0.1 v maximum clock frequency f max. 40 mhz h
data sheet s12595ej2v0ds00 13 m m m m pd16634a electrical characteristics (t a = C10 to +75 c, v dd1 = 3.3 v 0.3 v, v dd2 = 8.0 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit input leakage current i il 1.0 m a high-level output voltage v oh sthr(sthl),i o =0 ma v dd1 - 0.1 v low-level output voltage v ol sthr(sthl),i o =0 ma 0.1 v g -corrected supply current i g v 0 - v 9 = 8 v v 0 ,v 9 0.3 0.6 ma driver output current i voh v x =7 v, v out =1 v note1 - 0.5 ma i vol v x =1 v, v out =7 v note1 0.5 ma output voltage deviation note2 d v o input data : 00h to 3fh 5 20 mv average output voltage variation note3 d v av input data : 00h to 3fh 10 mv output voltage range v o input data : 00h to 3fh 0.1 v dd2 - 0.1 v logic part dynamic current consumption notes4,5 i dd1 v dd1, when with no load 0.5 3.5 ma driver part dynamic current consumption notes4,5 i dd2 v dd2, when with no load 2.2 8.0 ma notes 1. v x refers to the output voltage of analog output pins s 1 to s 300 . v out refers to the voltage applied to analog output pins s 1 to s 300 . 2. the output voltage deviation refers to the voltage difference between adjoining output pins when the display data is the same (within the chip). 3. the average output voltage variation refers to the average output voltage difference between chips. the average output voltage refers to the average voltage between chips when the display data is the same. 4. the stb cycle is defined to be 20 m s at f clk = 40 mhz. the typ. values refer to an all black or all white input pattern. the max. value refers to the measured values in the dot checkerboard input pattern. 5. refers to the current consumption per driver when cascades are connected under the assumption of svga single-sided mounting (10 units). switching characteristics (t a = - - - - 10 to +75 c, v dd1 = 3.3 v 0.3 v, v dd2 = 8.0 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit start pulse delay time t plh1 c l = 25 pf 13 20 ns driver output delay time t phl2 c l = 125 pf, r l = 4 k w note 3.7 8 m s t phl3 5.3 14 m s t plh2 3.0 8 m s t plh3 5.3 14 m s input capacitance c 1 sthr,sthl excluded, t a = 25 c 5.4 15 pf c 2 7.6 15 pf note load condition output c l c l c l r l r l r l r l = 1k w c l = 25pf c l r l c l h
data sheet s12595ej2v0ds00 14 m m m m pd16634a timing requirements (t a = - - - - 10 to +75 c, v dd1 = 3.3 v 0.3 v, v ss1 = v ss2 = 0 v, t r = t f = 8.0 ns) parameter symbol condition min. typ. max. unit clock pulse width pw clk 25 ns clock pulse low period pw clk (l) 6ns clock pulse high period pw clk (h) 6ns data setup time t setup1 6ns data hold time t hold1 6ns start pulse setup time t setup2 5ns start pulse hold time t hold2 5ns start pulse low period t spl 6ns pol2 setup time t setup3 6ns pol2 hold time t hold3 6ns stb pulse width pw stb 1 m s data invalid period t inv 1clk final data timing t ldt 2clk clk-stb time t clk-stb clk -? stb - 6ns stb-clk time t stb-clk stb - ? clk - 6ns time between stb and start pulse t stb-sth stb ? clk - 60 ns pol-stb time t pol-stb pol - or ? stb -- 5ns stb-pol time t stb-pol stb ? pol - or 6ns h h
data sheet s12595ej2v0ds00 15 m m m m pd16634a 11. switching characteristic waveform(r,/l= h) unless otherwise specified, the input level is defined to be 0.5 v dd1 . t hold3 v dd1 v ss1 t setup2 pol2 d n0 to d n5 v out clk sthr (1st dr.) sthl (1st dr.) stb pol t hold1 t setup1 t plh1 t stb-sth t r 90% 10% pw stb t ldt t inv t pol-stb hi-z t phl3 t plh3 t phl2 t plh2 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 t setup3 t hold2 pw clk(l) pw clk t spl t f 1 d 1 to d 6 d 1 to d 6 d 7 to d 12 d 289 to d 294 d 295 to d 300 d 301 to d 306 d 3067 to d 3072 d 7 to d 12 1025 1026 2 51 52 3 12 50 invalid invalid invalid invalid t stb-clk pw clk(h) target voltage 0.1v dd2 6-bit accuracy v dd1 v ss1 t stb-pol t clk-stb h
data sheet s12595ej2v0ds00 16 m m m m pd16634a 12. recommended mounting conditions the following conditions must be met for mounting conditions of the m pd16634a. for more details, refer to the semiconductor device mounting technology manual(c10535e). please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. m pd16634an- xxx : tcp(tab pack age) mounting condition mounting method condition thermocompression soldering heating tool 300 to 350 c, heating for 2 to 3 sec ; pressure 100g(per solder) acf (adhesive conductive film) temporary bonding 70 to 100 c ; pressure 3 to 8 kg/cm 2 ; time 3 to 5 sec. real bonding 165 to 180 c pressure 25 to 45 kg/cm 2 time 30 to 40secs(when using the anisotropy conductive film sumizac1003 of sumitomo bakelite,ltd). caution to find out the detailed conditions for mounting the acf part, please contact the acf manufacturing company. be sure to avoid using two or more mounting methods at a time.
data sheet s12595ej2v0ds00 17 m m m m pd16634a [memo]
data sheet s12595ej2v0ds00 18 m m m m pd16634a [memo]
data sheet s12595ej2v0ds00 19 m m m m pd16634a notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd16634a reference documents nec semiconductor device reliability/quality control system(c10983e) quality grades to necs semiconductor devices(c11531e) the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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